The error detection and correction technologies examined by the inventors of the present invention include the following technologies.
In recent years, with the trend to higher integration (miniaturization) and lower voltage in a semiconductor integrated circuit, the influence due to the occurrence of soft error has become a serious problem. The soft error mentioned here is a phenomenon in which recorded information is inverted by α ray or neutron.
As the measures against the soft error, utilization of an error correcting code such as ECC (Error Check and Correct) has been known. In particular, Patent document 1, Patent document 2 and others describe that means such as ECC is mounted on a semiconductor integrated circuit in order to improve soft error tolerance in DRAM, SRAM and system LSI. In such a system, a bit error correcting code has been generally used and an extended hamming code (SEC-DED code (Single Error Correcting-Double Error Detecting Code)) is mainly used at present. This code corrects a 1-bit error and detects a 2-bit error. Conventionally, 8-bit error correction data (parity) is added for each 64-bit data and the data is stored and reproduced in units of 72-bit data in total, and the code is called (72, 64) SEC-DED code.
However, since the soft error due to α ray ranges over multiple bits, multi-bit errors need to be handled and a code that performs the detection in units of b (b=4) bits is proposed. FIG. 6 is a block diagram of the error detection and correction system, in which 610 denotes encoded information, 620 denotes a check bit generation circuit, 650 denotes a main storage, 670 denotes a syndrome generation circuit, 690 denotes an error detection circuit, 6100 denotes a syndrome decoder, and 6120 denotes an error correction circuit. This system has a capability to detect a single block error of b (b=4) bits and is capable of 1-bit error correction and 2-bit error detection.
Furthermore, Patent document 3 proposes a configuring method and decoding method of a code called spotty byte error control code. This relates to a code and its decoding circuit for correcting a single spotty byte error and detecting two spotty byte errors. The spotty byte error mentioned here is the error up to t bits within one byte consisting of b bits (t≦b).    Patent document 1: Japanese Patent Application Laid-Open Publication No. 10-340586    Patent document 2: Japanese Patent Application Laid-Open Publication No. 2003-337760    Patent document 3: Japanese Patent Application Laid-Open Publication No. 2005-176244    Non-Patent document 1: Chikasi HORIKIRI, “No Time to Waste for Soft Error Countermeasures, SRAM and Logic Circuit Now Come under Scrutiny”, Nikkei Electronics, Nikkei Business Publication, Inc., Jul. 4, 2005, No. 903, pp. 63-70    Non-Patent document 2: Yoshiharu TOSAKA, “Reality of Soft Error You Need to Know: History, Evaluation Method and Countermeasures”, Nikkei Electronics, Nikkei Business Publication, Inc., Jul. 4, 2005, No. 903, pp. 145-156